This application claims priority from Korean Patent Application No. 2002-26438, filed May 14, 2002, which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for improving operational characteristics of dynamic random access memory (DRAM) cells by improving contact resistance and characteristics of transistors in manufacturing a semiconductor device having contact plugs that are self-aligned with gate electrodes.
2. Description of the Related Art
When manufacturing a highly integrated semiconductor device, such as DRAM, call areas decrease as a design rule decreases. Accordingly, because contact resistance and a short channel effect increase, the breakdown voltage of cell transistors decreases so that there is a limit in forming reliable cell transistors.
Meanwhile, in order to highly integrate a semiconductor device, such as DRAM, technology for forming contact plugs between gate electrodes by a self-aligned method has been developed to form a fine device, which is required in a highly integrated semiconductor device, regardless of precision in alignment between patterns. In a method for manufacturing a semiconductor device in a self-aligned manner, gate electrodes are patterned, impurity ions at a low dose are implanted, and spacers are formed on the sidewalls of the gate electrodes, so that impurity ions at a high dose are implanted so as to form source/drain regions of a lightly doped drain (LDD) structure. In addition, when manufacturing a device having a design rule of less than 0.2 xcexcm, a high doping implantation process for forming source/drain regions is generally performed after patterning an interlayer insulating layer for forming self-aligned contact holes. Here, in order to secure a sufficient breakdown voltage for obtaining desired operational characteristics of cell transistors in a highly integrated semiconductor device, a doping dose in a substrate has to be increased, or a sufficient effective channel length has to be secured to prevent a punch-through effect. However, a method of increasing a doping dose has a side effect of increasing a junction leakage current so that retention time suddenly falls. Consequently, in order to prevent the above problem, an effective channel length has to be increased by increasing the width of the gate electrodes or the width of the spacers formed on the sidewalls of the gate electrodes, while refraining from increasing the doping dose. However, this method is difficult to be applied when manufacturing a highly integrated semiconductor device. Furthermore, this method reduces contact areas between contact plugs and source/drain regions thereby increasing contact resistance so that cell failure occurs.
The present invention contemplates a method for manufacturing a highly integrated semiconductor device to improve the reliability of cell transistors by increasing an effective channel length while preventing contact areas between the source/drain and contact plugs from decreasing.
According to a first embodiment of the present invention, a plurality of gate structures including gate electrodes and insulating layers covering the gate electrodes are formed on a semiconductor substrate. Impurity ions at a low dose for forming a source/drain region are implanted into the semiconductor substrate using the gate structures as a mask. First insulating spacers are formed on the sidewalls of the gate structures. A liner is formed on the gate structures and on the first insulating spacers to form second insulating spacers. A planarized interlayer insulating layer pattern for defining holes between adjacent second insulating spacers, through which the semiconductor substrate is exposed, is formed on the gate structures. Impurity ions at a high dose for forming the source/drain are implanted into the semiconductor substrate, using the interlayer insulating layer pattern and the second insulating spacers as a mask. The second insulating spacers are removed.
It is preferable that the removal of the second insulating spacers is performed by a wet etching method using ozone water. To this end, a first wet etching process is performed using an etchant having the ozone water and a hydrogen fluoride (HF) solution. Thereafter, a second wet etching process is performed using the ozone water. It is preferable that the mixed solution of the ozone water and the HF solution be mixed at a volume ratio of about 1000:1 to about 1500:1.
The removal of the second insulating spacers may be performed by a down-stream plasma etching process using a gas mixture having oxygen (O2) and carbon fluoride (CF4). Here, O2 and CF4 is mixed at a flow ratio of about 10:1 to about 100:1 to form the gas mixture.
The method of manufacturing a semiconductor device according to the first embodiment of the present invention may further include forming a planarized interlayer insulating layer pattern for defining holes between the adjacent second insulating spacers, through which the semiconductor substrate is exposed, on the gate structures, and forming third insulating spacers on the sidewalls of the interlayer insulating pattern and the second insulating spacers. Here, the implantation of the impurity ions at a high dose is performed, using the interlayer insulating layer pattern and the third insulating spacers as a mask. The second insulating spacers and the third insulating spacers may be concurrently removed.
According to a second embodiment of the present invention, a plurality of gate structures including gate electrodes and insulating layers covering the gate electrodes are formed on a semiconductor substrate. Impurity ions at a low dose for forming source/drain are implanted into the semiconductor substrate using the gate structures as a mask. First insulating spacers are formed on the sidewalls of the gate structures. A planarized interlayer insulating layer pattern for defining holes, through which the low dose impurity ion implanted semiconductor device is exposed, is formed on the gate structures. Second insulating spacers are formed on the sidewalls of the interlayer insulating layer pattern and on the first insulating spacers. Impurity ions at a high dose for forming the source/drain are implanted into the semiconductor substrate, using the interlayer insulating layer pattern and the second insulating spacers as a mask. The second insulating spacers are removed.
Preferably, the first insulating spacers may be formed of silicon nitride layers. Alternately, the first insulating spacers comprise silicon nitride layers contacting the gate structures and silicon oxide layers formed on the silicon nitride layers.
The method for manufacturing a semiconductor device according to the second embodiment of the present invention may further include forming an oxide liner on the gate structures and on the first insulating spacers, after the first insulating spacers are formed, and additionally implanting impurity ions at a low dose into the semiconductor substrate, using the oxide liner as a mask.
In order to form the interlayer insulating layer pattern, a planarized interlayer insulating layer is formed on the semiconductor substrate, into which the impurity ions of low are additionally implanted, and on the oxide liner. The interlayer insulating layer is patterned to form the holes therein. The portions of the oxide liner are removed to expose the first insulating spacers while patterning the interlayer insulating layer.
According to a third embodiment of the present invention, gate electrodes are formed on a first region of a semiconductor substrate having the first region to form channels and a second region to form a source/drain region. Impurity ions at a low dose are implanted into the second region, using the gate electrodes as a mask. First insulating spacers are formed on the sidewalls of the gate electrodes to expose the second region to a first width in a first direction orthogonal to the lengthwise direction of the gate electrodes. A planarized interlayer insulating layer pattern for defining holes through which the first insulating spacers are exposed, is formed on the gate electrodes. Second insulating spacers are formed on the sidewalls of the interlayer insulating layer pattern and on the first insulating spacers to expose the second region to a second width, which is narrower than the first width. Impurity ions at a high dose are implanted into the second region, using the interlayer insulating layer pattern and the second insulating spacers as a mask. The second insulating spacers are removed to expose the second region to the first width.
The method for manufacturing a semiconductor device according to the third embodiment of the present invention may further include removing portions of the first insulating spacers to expose the second region to a third width, which is wider than the first width.
The method for manufacturing a semiconductor device according to the third embodiment of the present invention may further include forming a nitride liner on the first insulating spacers to expose the second region to a fourth width, which is narrower than the first width. Here, the second insulating spacers are formed on the nitride liner.
The method for manufacturing a semiconductor device according to the third embodiment of the present invention may further include forming an oxide liner on the first insulating spacers to expose the second region to a fourth width, which is narrower than the first width, and additionally implanting impurity ions at a low dose into the second region, using the oxide liner as a mask.
According to the present invention, channel length and contact areas are controlled using insulating spacers in manufacturing a highly integrated semiconductor device having contact plugs self-aligned with gate electrodes. Therefore, operational characteristics of DRAM cells can be improved by securing reliability of cell transistors, while preventing contact resistance of the semiconductor device from increasing.